The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, multilayer interconnects (MLI) are used to connect various devices (transistors, resistors, capacitors, etc.) to form an IC. In a typical multilayer interconnect structure, conductive lines (e.g., copper wires) are laid in stacked dielectric layers and are connected through vias from one layer to another layer. The process takes aligning multiple conductive features to overlying and underlying layers. The alignment can be defined by patterns fabricated with lithography (or photolithography) processes. Sometimes, overlay errors between lithography processes may result in via misalignment with respect to the target conductive features. A misaligned conductive feature may cause accidental bridge (shorting) with a nearby conductive feature(s), creating IC defects; cause excessive etching of the underlying layer(s), creating IC reliability issues; or cause misalignment between desired interconnections of conductive features thereby creating a risk of an open. Such conductive feature (e.g., via-wire) misalignment issues become more problematic as the IC miniaturization continues.